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Back-gated OFET Interdigitated Substrate Au source/drain, 90 nm SiO2 gate-insulator, varied W/L from 500 to 4000, 16 transistors per chip, chips (diced)

Back-gated OFET Interdigitated Substrate

Back-gated OFET Interdigitated Substrate Au source/drain, 90 nm SiO2 gate-insulator, varied W/L from 500 to 4000, 16 transistors per chip, chips (diced)

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FIPMS223

Back-gated OFET Interdigitated Substrate, Au source/drain, 90 nm SiO2 gate-insulator, varied W/L from 500 to 4000, 16 transistors per chip, chips (diced)