FIPMS176

Back-gated OFET Substrate

n-doped silicon wafer with 230 nm SiO2 gate-insulator, chips (diced)

• Code UNSPSC : 43211915
• Nomenclature NACRES : NA.23

Propriétés

• Forme: chips (diameter 200 mm); chips (diced)
• Conditionnement: pack of 1 (wafer of 112 diced chips)

Description

Description générale

Substrate: 200 mm wafer according to semiconductor standard (used for bottom-gate)
Layer structure:

• Gate: n-doped silicon (doping at wafer surface: n~3x1017/ cm³)
• Gate oxide: 230 nm ± 10 nm SiO₂ (thermal oxidation)
• Drain/source:none
• Protection: resist AR PC 5000/3.1 (soluble in AZ-Thinner or acetone)
• Layout: bare oxide but diced
• Chip size: 15 x 15 mm²
• No. of chips: 112 per wafer

Application

Back-gated OFET Substrate (organic field-effect transistor) can be used in the fabrication of chemical sensors for potential usage in pH sensing and detection of immunoassays. It can also be used in the fabrication of biosensors by coating the sheets of the FET with a specific antibody for the detection of SARS-CoV-2. FET based biosensors can be potentially used in clinical diagnosis, point of care testing, and on-site detection.

For material scientists in the field of organic semiconductors, it is critically important to have standardized device architecture for material analysis.

These back-gated organic filed-effect transistor (OFET) substrates were fabricated inside the cleanroom, and source and drain electrodes can be deposited either prior or after the deposition of an organic semiconductor material, giving versatility for the choice of source/drain materials and satisfy different preferred device architectures.

When an organic semiconductor layer is deposited on such a substrate, the bulk Si acts as gate electrode and controls the channel current between the post-deposited source and drain electrodes on the top. A suitably doped Si-SiO₂ interface in CMOS quality guarantees a reproducible gate contact.

Conditionnement

diced wafer on foil with air tight packaging

Notes préparatoires

Recommendation for resist removal:
To guarantee a complete cleaning of the wafer / chip surface from resist residuals, please rinse by acetone and then dry the material immediately by nitrogen (compressed air).

Recommendation for material characterization:
If gate currents appear during the characterization of the field effect transistors, considerable variations could occur at the extraction of the carrier mobility. Therefore it is necessary to check the leakage currents over the reverse side (over the chip edges) of the OFET-substrates.

Stockage et stabilité

Store the wafers at a cool and dark place and protect them against sun.Resist layer was applied to prevent damage from scratches. Expiration date is the recommended period for resist removal only. After resist removal, the substrate remains functional and does not expire.

Informations légales

Product of Fraunhofer IPMS