FIPMS223
Back-gated OFET Interdigitated Substrate
Au source/drain, 90 nm SiO2 gate-insulator, varied W/L from 500 to 4000, 16 transistors per chip, chips (diced)
Sign Into View Organizational & Contract Pricing
All Photos(4)
About This Item
UNSPSC Code:
43211915
NACRES:
NA.23
form
chips (diced)
packaging
pack of 1 (wafer of 60 diced chips)
storage temp.
15-25°C
Looking for similar products? Visit Product Comparison Guide
General description
Substrate: 150 mm wafer according to semiconductor standard (used for bottom-gate)
Layer structure:
4 x transistors L= 2.5 μm W= 10 mm
4 x transistors L= 5 μm W= 10 mm
4 x transistors L= 10 μm W= 10 mm
4 x transistors L= 20 μm W= 10 mm
Layer structure:
- Gate: n-doped silicon (doping at wafer surface: n~3x1017/ cm3)
- Gate oxide: 90 nm ± 10 nm SiO2 (thermal oxidation)
- Drain/source: 30 nm Au with 10 nm high work function adhesion layer (ITO), by lift-off technique
- Protection: resist AR PC 5000/3.1 (soluble in AZ-Thinner or acetone)
- Layout: see images
- Test chip size: 15 x 15 mm2
- No. of chips: 60 per wafer
- Contact pads: 0.5 x 0.5 mm2
- No. of transistors: 16 per chip
4 x transistors L= 2.5 μm W= 10 mm
4 x transistors L= 5 μm W= 10 mm
4 x transistors L= 10 μm W= 10 mm
4 x transistors L= 20 μm W= 10 mm
Application
Back-gated OFET Interdigitated Substrate (organic field-effect transistor) can be used in the fabrication of chemical sensors for potential usage in pH sensing and detection of immunoassays. It can also be used in the fabrication of biosensors by coating the sheets of the FET with a specific antibody for the detection of SARS-CoV-2. FET based biosensors can be potentially used in clinical diagnosis, point of care testing, and on-site detection.
Packaging
diced wafer on foil with air tight packaging
Preparation Note
Recommendation for resist removal:
To guarantee a complete cleaning of the wafer / chip surface from resist residuals, please rinse by acetone and then dry the material immediately by nitrogen (compressed air).
Recommendation for material characterization:
If gate currents appear during the characterization of the field effect transistors, considerable variations could occur at the extraction of the carrier mobility. Therefore it is necessary to check the leakage currents over the reverse side (over the chip edges) of the OFET-substrates.
To guarantee a complete cleaning of the wafer / chip surface from resist residuals, please rinse by acetone and then dry the material immediately by nitrogen (compressed air).
Recommendation for material characterization:
If gate currents appear during the characterization of the field effect transistors, considerable variations could occur at the extraction of the carrier mobility. Therefore it is necessary to check the leakage currents over the reverse side (over the chip edges) of the OFET-substrates.
Storage and Stability
Store the wafers at a cool and dark place and protect them against sun.
Resist layer was applied to prevent damage from scratches.
Expiration date is the recommended period for resist removal only. After resist removal, the substrate remains functional and does not expire.
Resist layer was applied to prevent damage from scratches.
Expiration date is the recommended period for resist removal only. After resist removal, the substrate remains functional and does not expire.
Legal Information
Product of Fraunhofer IPMS
Certificates of Analysis (COA)
Search for Certificates of Analysis (COA) by entering the products Lot/Batch Number. Lot and Batch Numbers can be found on a product’s label following the words ‘Lot’ or ‘Batch’.
Already Own This Product?
Find documentation for the products that you have recently purchased in the Document Library.
Our team of scientists has experience in all areas of research including Life Science, Material Science, Chemical Synthesis, Chromatography, Analytical and many others.
Contact Technical Service