High-Purity Sublimed Materials for Organic Electronic Devices

Ajay Virkar, Zhenan Bao

Department of Chemical Engineering, Stauffer III, 381 North-South Mall, Stanford University, Stanford, CA 94305-5025

Thin Film Transistor Device Preparation and Performance using Triple-Sublimed Pentacene

Introduction

Organic field-effect transistors (OFETs) have attracted considerable attention due to their potential for realizing large-area, mechanically flexible, lightweight and low-cost devices. One of the key components for performance in these devices is the organic semiconductor, and as such the design and purity of new semiconductor materials has been critical to the advancement of organic electronics technology. The highest mobility devices demonstrated in the literature have utilized small molecule semiconductors,¹ (as shown in the single crystal device² – Figure 1) or a blend of small molecule and polymer materials.³

Figure 1. Sublimed grade Rubrene (551112) in a single-crystal OFET setup², with an extremely high hole mobility of ~8 cm²/V.s.

High purity organic semiconductor material is preferable to achieve better properties (hole mobility and on/off ratio) in organic thin film transistors (OTFTs) and may help increase the device lifetime. The sublimation technique is a very good purification method and because a number of organic semiconducting materials (i.e. pentacene) sublime at high temperatures and high vacuum, higher purity materials can be obtained. An OTFT device was fabricated using a triple-sublimed grade of pentacene (698423), and the ultra high performance characteristics are reported in this note.

Figure 2. Schematic of an OTFT device showing the dielectric layer modified with crystalline OTS and Triple-Sublimed pentacene as the semiconductor (698423).

Device Preparation and Characterization

Pentacene thin film transistors were fabricated using triple-sublimed ≥99.995 % purity pentacene as the active material. Heavily n-doped silicon substrates with a thermally grown 300 nm silicon dioxide dielectric layer, and a capacitance per unit area (Ci) of 10 nF/cm² were used as transistor substrates (Silicon Quest Inc.). The Si/SiO₂ was cleaned in piranha solution (7:3 H₂SO₄: H₂O₂ CAUTION: highly reactive) for 30 minutes and then copiously washed with deionized water. A crystalline monolayer of octadecylsilane (OTS) (442291) was then deposited on the Si/SiO₂ wafer pieces to modify the dielectric surface. We have previously reported⁴ the details for the preparation of the crystalline OTS monolayer. Pentacene was then deposited via thermal evaporation at a rate of 0.3-0.4 Å/s, under a vacuum pressure of 10-6- 10-7 Torr with a substrate temperature of 60 ºC to obtain a final film thickness of 40 nm (as determined by a quartz crystal monitor in the evaporation chamber). Subsequently, gold electrodes (~40 nm in thickness) were deposited using shadow masks with a W/L of 20 (W = channel width, L = channel length), where L = 50-150 μm.

The electrical characteristics of the pentacene transistors were obtained at room temperature in ambient conditions using a Keithley 4200 (Hewlett-Packard) semiconductor parameter analyzer. Transfer current-voltage (IV) characteristics were obtained with a fixed source-drain voltage of -100 V.

Results

Representative transfer IV curves are shown below:

Figure 3. Representative transfer IV curves of OTFT devices (Left- Device #3 and Right- Device #5 in Table 1) with Triple sublimed pentacene (698423).

Figure 4. Output IV curves of a Triple-Sublimed pentacene (698423) OTFT (Device #1).

Note that the transfer curves in Figure 3, the on/off ratios are in excess of 10⁶. The charge carrier mobility was calculated from the saturation transfer IV curves (Figure 4) using the relationship:

I_DS = (WC/2L)µ (V_g - V_t)²

Where μ is the charge carrier mobility, I_DS is the drain current, V_G is the gate voltage , V_T is the threshold voltage and C is the capacitance. The channel geometry is defined by the (channel width (W) and length (L)).

The key transistor metrics (mobility, on/off and threshold voltage) for seven OTFTs fabricated using Triple-Sublimed Pentacene are given below:

Table 1. Performance of seven transistors fabricated using Triple-Sublimed pentacene.

Device	(cm2/Vs)	On/Off	VT (V)
1	1.1	105	-22
2	4	7x106	-17
3	4.6	5.6x106	-22
4	2.1	1.2x106	-16
5	3.2	1.1x107	-18
6	4.4	1.3x107	-21
7	4.5	2.4x107	-18
Average (stdev)	3.4 (1.3)	8x106	-19 (2.4)

Summary

Pentacene organic thin film transistors (OTFTs) were fabricated using triple-sublimed ≥99.995 % purity pentacene. On crystalline octadecylsilane modified SiO₂ dielectric surface the average charge carrier mobility was 3.4 cm²/Vs (max 4.6 cm²/Vs). The extremely high performance of the OTFTs is attributed to the high purity of the pentacene, and the crystalline dielectric modification layer.

We offer a selection of high-purity sublimed materials, suitable for a wide range of organic electronics applications. In order to consistently offer the highest quality materials, sublimed grade products are subject to extensive purity testing, which can include:

1. Trace Metals Analysis
2. DSC / TGA
3. HPLC (if the material is soluble)

Product specific testing information can be found on the specification sheet or the Certificate of Analysis.

References

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2. Podzorov V, Menard E, Rogers JA, Gershenson ME. Hall Effect in the Accumulation Layers on the Surface of Organic Semiconductors. Phys. Rev. Lett.. 95(22): https://doi.org/10.1103/physrevlett.95.226601

3. McCulloch I, Heeney M, Chabinyc ML, DeLongchamp D, Kline RJ, Cölle M, Duffy W, Fischer D, Gundlach D, Hamadani B, et al. 2009. Semiconducting Thienothiophene Copolymers: Design, Synthesis, Morphology, and Performance in Thin-Film Organic Transistors. Adv. Mater.. 21(10-11):1091-1109. https://doi.org/10.1002/adma.200801650

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