Skip to Content
Merck
  • Vertically integrated logic circuits constructed using ZnO-nanowire-based field-effect transistors on plastic substrates.

Vertically integrated logic circuits constructed using ZnO-nanowire-based field-effect transistors on plastic substrates.

Journal of nanoscience and nanotechnology (2013-07-19)
Jeongmin Kang, Taeho Moon, Youngin Jeon, Hoyoung Kim, Sangsig Kim
ABSTRACT

ZnO-nanowire-based logic circuits were constructed by the vertical integration of multilayered field-effect transistors (FETs) on plastic substrates. ZnO nanowires with an average diameter of -100 nm were synthesized by thermal chemical vapor deposition for use as the channel material in FETs. The ZnO-based FETs exhibited a high I(ON)/I(OFF) of > 10(6), with the characteristic of n-type depletion modes. For vertically integrated logic circuits, three multilayer FETs were sequentially prepared. The stacked FETs were connected in series via electrodes, and C-PVPs were used for the layer-isolation material. The NOT and NAND gates exhibited large logic-swing values of -93%. These results demonstrate the feasibility of three dimensional flexible logic circuits.

MATERIALS
Product Number
Brand
Product Description

Supelco
Zinc oxide, analytical standard
Sigma-Aldrich
Zinc oxide, 99.999% trace metals basis
Sigma-Aldrich
Zinc oxide, dispersion, nanoparticles, <100 nm particle size (TEM), ≤40 nm avg. part. size (APS), 20 wt. % in H2O
Sigma-Aldrich
Zinc oxide, 99.99% trace metals basis
Sigma-Aldrich
Zinc oxide, nanopowder, <100 nm particle size
Sigma-Aldrich
Zinc oxide, nanopowder, <50 nm particle size (BET), >97%
Sigma-Aldrich
Zinc oxide, ReagentPlus®, powder, <5 μm particle size, 99.9%
Sigma-Aldrich
Zinc oxide, puriss., meets analytical specification of Ph. Eur., BP, USP, 99-100.5% (calc. for dried substance)
Sigma-Aldrich
Zinc oxide, puriss. p.a., ACS reagent, ≥99.0% (KT)